For most of conventional processors, address register file thereof includes a plurality of address registers. In view of algorithmic requirements, there is a corresponding address increment register for each address register. The address register automatically increases or decreases aa_inc after every implementation of the load/store instruction, where the aa_inc is an automatic-increment value or an automatic-decrement value of the address increment register. The load and store instructions can be performed continuously due to the presence of the aa_inc so as to load or store different address data without writing an address operation instruction. Additionally, the address buffer management needs to be implemented in the communication algorithms such as LTE, i.e., to set a leading boundary value and a trailing boundary value of an address register so that the address automatically increases or decreases in a range between the leading boundary value and the trailing boundary value, and automatically returns to the range when the address is out of the range.
The arithmetic logic of a conventional solution for implementing the address buffer management is to set two boundary registers for each address register of which one is a leading boundary register and another is a trailing boundary register, and to set respective values of the two registers through instructions. When a load or store instruction is performed a current address value is added with the automatic-increment value and then is compared with the boundary values, if the increased address value is out of the range between the boundary values, the address will return into the range. The encoding corresponding to the arithmetic logic is classed into two groups as follows:
(1) the encoding in the case that the address automatically increases:
if(aa_inc >=0&&aa + aa_inc>aa_end)  aa=aa+aa_inc−(aa_end−aa_start+1);else  aa=aa + aa_inc;
(2) the encoding in the case that the address automatically decreases:
if(aa_inc < 0&&aa + aa_inc<aa_start)  aa=aa+aa_inc+(aa_end − aa_start+1);else  aa=aa + aa_inc;where aa_inc is the automatic-increment value or the automatic-decrement value of the address increment register (aa_inc is the automatic-increment value of the address increment register when the address automatically increases, and the aa_inc is the automatic-decrement value of the address increment register when the address automatically decreases), the aa_start is the leading boundary value of the address buffer, the aa_end is the trailing boundary value of the address buffer, the aa is the current value of the address register, and (aa_end−aa_start+1) is a buffer size value of the address register.
However, in the conventional solution, the arithmetic logic is performed in a processor. That is, for the following four operations aa+aa_inc>aa_end, aa+aa_inc<aa_start, aa+aa_inc+(aa_end−aa_start+1) and aa+aa_inc−(aa_end−aa_start+1), it is necessary to apply a circuit composed of two adders in series and a two-grade MUX (i.e. a 2-to-1 MUX to implement selective output) on the processor's hardware, so as to implement the address buffer management, wherein the circuit is referred as four key paths shown by heavy lines in FIG. 1. Therefore, it is obvious that the logical circuit of the processor is complex.
Specifically, in FIG. 1, ⊕ indicates an adder (to perform an addition operation in the above encoding), indicates a MUX (to perform if/else, i.e. the branch selecting operation in the above encoding), which also be referred to as a branch selector, and buffsize=aa_end−aa_start+1. In the solution as shown in FIG. 1, two adders are connected in series, such as an adder 11 is connected in series with an adder 12, and the adder 11 is connected in series with an adder 13. A two-grade MUX circuit is used in FIG. 1, such as a MUX 21 (a MUX 22) and a MUX 23 form the two-grade MUX, that is, the two-grade MUX circuit is used to implement the selective output.
In view of the above, in order to perform serial processing of the logical circuit of the processor, it is necessary to connect two adders in serial, and in order to implement the selective output, it is necessary to use a two-grade MUX circuit. As can be seen, the complex logical operations results in a complex logical circuit of the processor, which increases hardware costs. Moreover, the complex logical operations pull down the frequency of the processor and cause a time sequence problem. And thus, the solution for implementing address buffer management using the conventional processor increases the hardware costs and cannot meet design requirements of the processor's time sequence and energy efficiency.